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| st ST2205U preliminary 8 bit integrated microcontroller with 32k bytes ram notice:sitronixtechnologycorp.reservestherigh ttochangethecontentsinthisdocumentwithoutp riornotice. thisisnotafinalspecification. someparametersaresubjecttochange. version1.0 1/32 6/13/2007 1 1 . . f f e e a a t t u u r r e e s s totally static 8-bit cpu rom: 16k x 8-bit(otp) ram: 32k x 8-bit stack: up to 128-level deep operation voltage: 2.4v ~ 3.6v operation frequency: C4.0mhz@2.4v(min.) C6.0mhz@2.7v(min.) one 16x8 signed multiplier low voltage reset (lvr) Ctwolevelsofbondingoptions low voltage detector (lvd) Cprogrammable4levels Csystempowerorexternalbatterylevelcanbedet ected. flash memory interface Contheflyecccodegenerationanddetection Cfastdatatransferwithdedicateddmachannel Cnandandandtypeflashsupported usb 2.0 full speed device Cintegrateoneplltoproduce48mhzclock Cbuiltin3.3vregulatorfortransceiver Cmassstorageclasssupported Cdoublebufferinganddirectbufferaccessincreas e throughputandeaserealtimedatatransfer direct memory access (dma) Ctwochannelswithspecialmodesforflashanddis play Cthreeaddressgenerationmodes memory configuration Cfourkindsofbanksforbios,program,data,inte rrupt andinternalram C13bitbankregisterssupportupto44mbytes Csixprogrammablechipselectswith4modes Cmaximumsingledeviceof16mbytes Cbuildinawaitingcycleinexternalmemoryi/fs timing canbeselectedtosupportlowspeeddevice. general-purpose i/o (gpio) ports C56multiplexedcmosbitprogrammablei/os Chardwaredebounceoptionforporta Cbitprogrammablepullup/downoropendrain/cmos timer/counter Cfour12bitandone8bittimers Csevenfixedtimebases watchdog timer (wdt) Ctwoselectabletimebases Cprogrammablewdtinterruptorreset real-time clock (rtc) Cfullclockfunction,second/minute/hourandday ,with threecountersandinterrupts Coneprogrammablealarm three external interrupt sources three clocking outputs Cclocksourcesincludingtimer0,oscnclock,baud rate generator prioritized interrupts with dedicated exception vec tors Cexternalinterrupts(x3)(edgetriggered) Cportainterrupt(transitiontriggered) Clcdbufferinterrupt Cbasetimerinterrupt(x8) Ctimer0~3interrupts(x4) Cspiinterrupts(x2) Cuartinterrupts(x2) Cusbinterrupts(x6) Cpcminterrupt Crtcinterrupts(x4) dual clock sources with warm-up timer Clowfrequencycrystaloscillator(oscx) 32768hz Chighfrequencyresistororcrystal/resonatorosci llator (osc)selectedbypinoption .................. 455k~ 8mhz lcd controller (lcdc) Cprogrammabledisplaysize: com:512max. seg:1024max. max.160xrgbx120colorstnsupportedbyinternal buffer Chardware4/16graylevelswith5bitpalette,up to4096 colorssupported Csharesystemmemorywithdisplaybufferandwith no lossofthecputime Csupport1/4/8bitlcddatabus Cdiversefunctionsincludingvirtualscreen,panni ng, scrolling,contrastcontrol,alternatingsignalgen erator, bufferswitchingandfastgraphicdatamanipulation programmable sound generator (psg) Cfourchannelswiththreeplayingmodes: 9bitadpcm,8bitpcmand8bitmelody Cone16bytebufferand6bitvolumecontrolperc hannel Cwavetablemelodysupport Ctwodedicatedpwmoutputsfordirectdriving
ST2205U version1.0 2/32 6/13/2007 12-bit current dac with two 4-word buffer universal asynchronous receiver/transmitter (uart) Cfullduplexoperation Cbaudrategeneratorwithonedigitalpll Cstandardbaudratesof600bpsto115.2kbps Cbothtransmitterandreceiverbufferssupported Cdirectgluelesssupportofirdaphysicallayerpr otocol Ctwosetsofi/os(tx,rx)fortwoindependentdevi ces serial peripheral interface (spi) Cintericsound(iis)supported Cmasterandslavemodes Cfiveserialsignalsincludingenableanddatarea dy Cbothtransmitterandreceiverbufferssupported Cprogrammabledatalengthfrom7bitto16bit three power down modes Cwai0mode Cwai1mode Cstpmode on-chip ice debug interface 2 2 . . g g e e n n e e r r a a l l d d e e s s c c r r i i p p t t i i o o n n theST2205Uisa8bitintegratedmicrocontrollerd esigned withcmossilicongatetechnology.thetruestatic cpucore, powerdownmodesanddualoscillatorsdesignmakes the ST2205Usuitableforpowersavingandlongbattery life designs.theST2205Uintegratesvariouslogictosu pport functionsonchipwhichareneededbysystemdesign ers.this isalsoimportantforlowersystemcomplexity,smal lboardsize and,ofcourse,shortertimetomarketandlesscos t. theST2205Ufeaturesthecapacityofmemoryaccess of maximum44mbyteswhichisneededbyproductswith large databases.sixchipselectsareequippedfordirec tconnection toexternalrom,sram,flashmemoryorotherdevice s. maximumonesingledeviceof16mbytesispossible. twodmachannelsmakefastdatatransferpossiblea ndeasy. bothsourceanddestinationpointerscanrefertot hewhole memoryspacewith15bitpointersandbankregister s.besides normaloperation,twospecialmodesaredesignedfo rdouble transferspeedofnandflashmemoryandalsofastg raphic operationbetweentwodisplaypictures. nandflashisalowcostmassdatastoragesolution fornewly design.theST2205Uequipsanandflashinterfacet oconnect bothnandandandflashmemories.botheccgenerati ngand checkingfunctionsaresupported.theseareveryim portantfor flashdatamanagement. theST2205Uhas56i/osgroupedinto7ports,port a~portf andportl.eachpincanbeprogrammedtoinputor output. therearetwooptions:pullup/downforinputsofp ortcand onlypullupforinputsoftheotherports.incase ofoutput, thereareopendrain/cmosoptionsforoutputsofpo rtcand onlycmosforotherports.portaisdesignedfork eyboard scanwithdebounceandtransitiontriggeredinterr upt,while portc/d/e/f/laresharedwithothersystemfunctio ns.allthe propertiesofi/opinsarestillprogrammablewhen theyare assignedtoanotherfunction.thisenlargesthefle xibilityofthe usageoffunctionsignals. theinternal32kbytesramhelpstodrivelargelcd panels upto160xrgbx120.togetherwith16graylevelsuppo rt,the ST2205Ucanrichdisplayinformationandthedivers ityof contentsaswell.thisisdonewithnoneedofexte rnaldisplay rambecauseofthespecialinternalmemorysharing design. thevariabledisplaybuffertechniquealsomakelar gepanel sizewithsmallinternalrampossible.usermayfre emajor internalramfortemporarycomputingoraccesswhil ekeeping thedisplaycontentcorrect. theST2205Uequipsserialcommunicationportsofon euart andonespitoperformdifferentcommunications,ex .:rs232 andirda,withsystemcomponentsorotherproducts suchas pc,notebook,andpopularpda.twoclockingoutputs can producesynthesizedpwmsignalsorhighfrequencyc arrierfor irremotecontrol.thishelpsproductsbecomemore usefulin ourdailylife. communicationwithpcviausbisbecomingmoreand more popular.theST2205Ufeaturesonepll,a3.3vregul ator,and ausb2.0fullspeeddeviceenginetosatisfythes trong demandoffastdatatransferfrommarket.bothhid andmass storageclassesaresupportedaswellasthefirmwa relibraries andthewindowsdrivers. thebuiltinfourchannelspsganda12bitcurrent dac provideanicequalityvoicetogetherwitha4chan nel wavetablemelodyinthebackground.bothvoiceand melody functionshavebufferstomakeprogrameasierandw ell structured,andalsoa16x8multiplieristocontro lthevolumnof eachchannel.besideshardware,adpcmalgorithmand a midiconverterwindowssoftwarearealsoprovidedt ospeed upthedevelopment.inadditiontocurrentdac,two dedicated pinswithlargedrivingcapacitycandriveabuzzer /speaker directlyforminimumcost. thest2205hasonelowvoltagedetector(lvd)forp ower management.thestatusofinternalorexternalpowe rcanbe detectedandreportedtothemanagementsoftware. powerbouncingduringpoweronisamajorproblemw hen designingareliablesystem.theST2205Uequipslow voltage reset(lvr)functiontokeepwholesysteminreset status whenpowerislow.afterthepowerbackstonormal, the systemmayrecoveritsoriginalstatesandkeepswo rking correctly.besideslvr,watchdogtimer(wdt)isal sobuiltin andisanessentialfunctionforagooddesign. powerconsumptionisanotherbigissueforabatter ypowered device.theST2205Uhasdifferentpowerdownmodes and clockswitchschemetomaketheconsumingpoweras lowas possible.thebuiltinrealtimeclock(rtc)isnot onlyfor keepingtimecorrectlybutalsoanalternativeofs oftwaretimer withmuchlowerworkingpower. theST2205Uequipsanicedebuginterfaceforeffic ient developmentflow.besideshardwareemulator,asoft ware simulatorisalsosupportedtosaveprogrammersset tingupthe systemandmakesprogrammingbeatanywhere. ST2205U version0.1 2/32 6/13/2007 withtheseintegratedfunctionsinside,theST2205U singlechip microcontrollerisarightsolutionforpda,transl ator,databank andotherconsumerproducts. cs0 /pd5 /a23 cs6 0 ~ /pd4 1 ~ cs5 wr rd /pc4 ss /pc5 data_ready blank poff /pd7 fwr /pd6 frd figure 2-1 ST2205U block diagram ST2205U version1.0 3/32 6/13/2007 3 3 . . s s i i g g n n a a l l d d e e s s c c r r i i p p t t i i o o n n s s table 3-1 signal function groups function group pad no. designation description power 11,61,83, 84,100, 104,117 132 vdd,iovdd,avdd psgvdd,usbvdd pllvdd,vpp vdd: powersupplyforinternalcore iovdd: powersupplyforio avdd: powersupplyforanalogblocks psgvdd: powersupplyforpsgoandpsgob usbvdd: powersupplyforusbcircuit pllvdd: powersupplyforpllcircuit vpp: powersupplyforprogrammingotprom ground 10,40,85, 96,103, 105,114, 129 vss,iovss,avss1 avss2,psgvss, usbvss,pllvss vss: powergroundforinternalcore iovss: powergroundforio avss: powergroundforanalogblocks psgvss: powergroundforpsgoandpsgob usbvss: powergroundforusbcircuit pllvss: powergroundforpllcircuit systemcontrol 1,30,68,86 87,115,116 120, 124~128 reset , test1/2/3, ice1/2/3/4/5/6, mmd/ cs0 ,lvrsel vin reset : activelowsystemresetsignalinput test1/2/3, ice1/2/3/4/5/6: leavethemopenwhennormaloperation mmd/cs0: memorymodesselectionpin normal mode: enableinternalrom. mmd/ cs0 connectstognd. emulation mode: disableinternalrom. mmd/ cs0 connectstochipselectpinofexternalrom.one resistorshouldbeaddedbetweenvccandthispin. afterreset cycles,mmd/ cs0 changestobeanoutput,andoutputssignal cs0 . lvrsel :lvractivelevelselectioninput low: lvractivelevelis2.1v high: lvractivelevelis2.8v vin :inputvoltagelevelforlowvoltagedetection clock 118,119, 121~123 xmd, xio,osci oscxo,oscxi xmd: highfrequencyoscillator(osc)modeselectioninp ut low: crystalmode onecrystalorresonatorshouldbeconnectedbetwee nosci andxio high: resistoroscillatormode oneresistorshouldbeconnectedbetweenosciandv cc oscxi, oscxo: connectone32768hzcrystalbetweenthesetwo pinswhenusinglowfrequencyoscillator 29,31 wr , rd externalmemoryr/wcontrolsignals 41~60, 62~64 a[22:0] externalmemoryaddressbus externalmemory bussignals 32~39 d[7:0] externalmemorydatabus pwmdac currentdac 130,131 psgo/cout, psgob psgo/psgob: psgoutputs.connecttoonebuzzerorspeaker cout: also12bitcurrentdacoutputbyregistercontrol keyboardscan signal(return line) 106~113 pa7~0 i/oporta gpio 2,88~95 pb7~0 pc0 i/oportbandpc0 ST2205U version1.0 4/32 6/13/2007 table 3-2 signal function groups (continued) function group pad no. designation description flashdatabus 65~67, 69~73 fd7~0/pf7~0 flashdatabus flashread/write signals 27,28 rxd1/ fwr /pd7 txd1/ frd /pd6 whenfunctionbitsareset,andi/odirectionisou tput,andfen=1, pd7/6areflashcontrolsignals chipselects 21~26 1 ~ cs5 /pd4~0, cs6 /a23/pd5 i/oportdandchipselectoutputs uart 8,9 27,28 rxd0/pc7,txd0/pc 6,rxd1/ fwr /pd7 txd1/ frd /pd6 uartsignalsandi/os spi 3~7 data_ready /pc5, ss /pc4,sdo/pc3, sdi/pc2,sck/pc1 spisignalsandi/os clockingoutput/ externalclock inputorinterrupt sources 13~15 bco/intx2/pe2, oscn/intx1//pe1 tco0/intx0//pe0 whenfunctionbitsareset,andi/odirectionisou tput,thesethree canbeclockingoutputs. whenfunctionbitsareset,andi/odirectionisin put,thesethree canbeexternalclockinputsorexternalinterrupt sources. whenfunctionbitsarecleared,theyarethreegpio s. lcdcontrol signals 12,16~20, 74~82 flm/pl7,lp1/pl6, ac/pl5,cp/pl4, ld[3:0]/pl3~0, ld[7:4]/pe6~3, lp2/pe7, poff , blank , lcdcontrolsignals usb2.0full speed 97~99,101 102 vbus, rpull,vout3.3, d+,d vbus: connecttousbbuspower d+,d-: usbdifferentialsignalpins rpull: addaresistorof1.5kbetweenthispinandd+ vout3.3: 3.3vregulatoroutput.connecttousbvddtosupply powerfortheanalogtransceiverofusb ST2205U version1.0 5/32 6/13/2007 4 4 . . p p a a d d d d i i a a g g r r a a m m ST2205U version1.0 6/32 6/13/2007 5 5 . . d d e e v v i i c c e e i i n n f f o o r r m m a a t t i i o o n n 1. pad size: 90um x 90um 2. substrate: gnd 3. chip size: 3490um x 4070um pad no. symbol x y 1 ice6 1465.1 1965.0 2 pc0 1345.1 1965.0 3 pc1 1245.1 1965.0 4 pc2 1145.1 1965.0 5 pc3 1045.1 1965.0 6 pc4 945.1 1965.0 7 pc5 845.1 1965.0 8 pc6 745.1 1965.0 9 pc7 645.1 1965.0 10 vss 545 .1 1965.0 11 vdd 345.1 1965.0 12 blank 245.1 1965.0 13 pe0 145.1 1965.0 14 pe1 45.1 1965.0 15 pe2 55.0 1965.0 16 pe3 155.0 1965.0 17 pe4 255.0 1965.0 18 pe5 355.0 1965.0 19 pe6 455.0 1965.0 20 pe7 555.0 1965.0 21 pd0 655.0 1965.0 22 pd1 755.0 1965.0 23 pd2 855.0 1965.0 24 pd3 955.0 1965.0 25 pd4 1055.0 1965.0 26 pd5 1155.0 1965.0 27 pd6 1255.0 1965.0 28 pd7 1355.0 1965.0 29 wr 1475.0 1965 .0 30 mmd/ cs0 1675.0 1940.0 31 rd 1675.0 1820.0 32 d7 1675.0 1700.0 33 d6 1675.0 1600.0 34 d5 1675.0 1500.0 35 d4 1675.0 1400.0 pad no. symbol x y 36 d3 1675.0 1300.0 37 d2 1675. 0 1200.0 38 d1 1675.0 1100.0 39 d0 1675.0 1000.0 40 iovss 1675.0 900.0 41 a0 1675.0 800.0 42 a1 1675.0 700.0 43 a2 1675.0 600.0 44 a3 1675.0 500.0 45 a4 1675.0 400.0 46 a5 1675.0 300.0 47 a6 1675.0 200.0 48 a7 16 75.0 100.0 49 a17 1675.0 0.0 50 a18 1675.0 100.0 51 a19 1675.0 200.0 52 a20 1675.0 300.0 53 a21 1675.0 400.0 54 a22 1675.0 500.0 55 a8 1675.0 600.0 56 a9 1675.0 700.0 57 a10 1675.0 800.0 58 a11 1675.0 900.0 59 a12 1675.0 1000.0 60 a13 1675.0 1100.0 61 iovdd 1675.0 1200.0 62 a14 1675.0 1300.0 63 a15 1675.0 1400.0 64 a16 1675.0 1500.0 65 pf0 1675.0 1600.0 66 pf1 1675.0 1700.0 67 pf2 1675.0 1820.0 68 test1 1675.0 1940.0 69 pf3 1475.0 1965.0 70 pf4 1355.0 1965.0 ST2205U version1.0 7/32 6/13/2007 pad no. symbol x y 71 pf5 1255.0 1965.0 72 pf6 1155.0 1965.0 73 pf7 1055.0 1965.0 74 pl0 955.0 1965.0 75 pl1 855.0 1965.0 76 pl2 755.0 1965.0 77 pl3 655.0 1965.0 78 pl4 555.0 1965.0 79 pl5 455.0 196 5.0 80 pl6 355.0 1965.0 81 pl7 255.0 1965.0 82 poff 155.0 1965.0 83 vpp 55.0 1965.0 84 vdd 45.0 1965.0 85 vss 245.0 1965.0 86 test2 345.0 1965.0 87 test3 445.0 1965.0 88 pb0 545.0 1965.0 89 pb1 645.0 1 965.0 90 pb2 745.0 1965.0 91 pb3 845.0 1965.0 92 pb4 945.0 1965.0 93 pb5 1045.0 1965.0 94 pb6 1145.0 1965.0 95 pb7 1245.0 1965.0 96 usbvss 1438.0 1965.0 97 rpull 1656.1 1965.0 98 d+ 1675.0 1764.7 99 d 1675.0 1644.7 100 usbvdd 1675.0 1532.7 101 vout3.3 1675.0 1422.7 102 vbus 1675.0 1232.7 103 avss2 1675.0 1075.8 104 pllvdd 1675.0 975.8 105 pllvss 1675.0 875.8 pad no. symbol x y 106 pa0 1675.0 747.1 107 pa1 1675.0 647.1 108 pa2 1675.0 547.1 109 pa3 1675.0 447.1 110 pa4 1675.0 347.1 111 pa5 1675.0 247.1 112 pa6 1675.0 147.1 113 pa7 1675.0 47.1 114 avss1 1675.0 53.0 115 vin 1675.0 153.0 116 lvrsel 1675.0 253.0 117 avdd 1675.0 353. 0 118 oscxi 1675.0 453.0 119 oscxo 1675.0 553.0 120 reset 1675.0 653.0 121 osci 1675.0 753.0 122 xio 1675.0 853.0 123 xmd 1675.0 953.0 124 ice3 1675.0 1053.0 125 ice2 1675.0 1153.0 126 ice1 1675. 0 1253.0 127 ice4 1675.0 1353.0 128 ice5 1675.0 1453.0 129 psgvss 1675.0 1553.0 130 psbo 1675.0 1673.0 131 psgob 1675.0 1793.0 132 psgvdd 1675.0 1913.0 ST2205U version1.0 8/32 6/13/2007 6 6 . . i i n n t t e e r r r r u u p p t t c c o o n n t t r r o o l l l l e e r r theST2205Usupports16hardwareinterruptsaswell asone softwareinterruptbrk.thereare17exceptionvect orsforthese interruptsandanotheroneforreset.allinterrupt sarecontrolled byinterruptdisableflag i (bit2ofstatusregister p ).hardware interruptsarefurthercontrolledbyinterruptenab leregister iena .settingbitsof iena enablesrespectiveinterrupts. theinterruptcontrollerownsonepriorityarbitrat or.whenmore thanoneinterruptshappenatthesametime,theon ewith lowerprioritynumberwillbeexecutedfirst.refer totable61 forprioritiesofinterrupts. onceaninterrupteventwasenabledandthenhappen s,the cpuwakesup(ifineitherwaitmode),andassociat edbitof interruptrequestregister( ireq )willbeset.if i flagiscleared, therelatedvectorwillbefetchedandthentheint erruptservice routine(isr)willbeexecuted.interruptrequestf lagcanbe clearedbytwomethods.oneistowrite0to ireq ,theother istoinitiaterelatedinterruptserviceroutine.h ardwarewill automaticallycleartheinterruptrequestflag.all interrupt vectorsarelistedintable61. table 6-1 interrupt vectors name signal source vector address priority description brk internal $7fff,$7ffe 1 softwarebrkoperationv ector reset external $7ffd,$7ffc 0 resetvector $7ffb,$7ffa reserved intx external $7ff9,$7ff8 9 pe0/1/2edgeinterrupt t0 internal/external $7ff7,$7ff6 10 timer0interrupt t1 internal $7ff5,$7ff4 11 timer1interrupt t2 internal/external $7ff3,$7ff2 12 timer2interrupt t3 internal $7ff1,$7ff0 13 timer3interrupt pt external $7fef,$7fee 14 portatransitioninterr upt bt internal $7fed,$7fec 15 basetimerinterrupt lcd internal $7feb,$7fea 16 lcdbufferinterrupt stx external $7fe9,$7fe8 1 spitransmitbufferempt yinterrupt srx external $7fe7,$7fe6 2 spireceivebufferready interrupt utx external $7fe5,$7fe4 3 uarttransmitterinterru pt urx external $7fe3,$7fe2 4 uartreceiverinterrupt usb external $7fe1,$7fe0 5 usbinterrupt reserved $7fdf,$7fde 6 pcm internal $7fdd,$7fdc 7 pcminterrupt rtc internal $7fdb,$7fda 8 rtcinterrupt ST2205U version1.0 9/32 6/13/2007 7 7 . . g g p p i i o o theST2205Uconsistsof48generalpurposei/o(gpi o)which aredividedintosixi/oports:porta/b/c/d/eand portl. eachsinglepincanbeprogrammedtobeinputorou tput.this iscontrolledbyportdirectioncontrolregisters pcx .settingbit of pcx makesrespectivepintooutput,andclearingthis bitfor input.therearetwooptions:pullup/downforinpu tsofportc butonlypullupforinputsoftheotherports.in caseofoutput, thereareopendrain/cmosoptionsforoutputsofpo rtcbut onlycmosfortheotherports.refertotable71. table 7-1 i/o types of gpio ports i/o types i/o mode port-a/b/d/e/l port-c input pullup/pure pullup/pulldown/pure output cmos opendrain/cmos input mode incaseofinputfunction,portdataregisters px reflectthe valuesonassociatedpins.besidesreadinstruction fordataof signalsinput,writingtoregister px selectsi/otypesofpins, pulluporpulldown.settingbitsofallportdata register px to selectpulluptype.clearingbitsofonly pc toselectpulldown typeforpinsofportc.therearenopulldownres istorsfor porta/b/d/eandportl,therebynopulldownresis torswillbe enabledifclearingbitsof pa , pb , pd , pe and pl .pullup resistorsofporta/b/d/e/larealsocontrolledby pullbit(bit7 ofportmiscellaneousregister pmcr ),0istodisable,while 1istoenablethem.thepullup/pulldownresist orsofportc arefurthercontrolledbybitsofporttypeselect registers psc . theyworkinthesamewaywithpullbitof pmcr butonlyon singlepin,0istodisable,while1istoenab le. vcc portdata register (pdr) pullup pmos pullup rd_input datainput portcontrol register (pcr) figure 7-1 configuration of port-a/b/d/e/l output mode incaseofoutputfunction,writetoportdataregi sters px makespinstooutputdesiredvalue.thisvaluecan alsobe readbackbyreadinstruction.besidesportc,the outputpins arecmostype.portchavetwooptionsofoutputty pes: opendrainandcmos,andiscontrolledbyporttype select registers psc .clearingbitsofregisters psc isforthatdisable pmosofoutputstageandleftonlynmos,whilesett ingbitsis forcmos. portaisdesignedforkeyboardscanwithdebounce and transitiontriggeredinterrupt,whileportc/d/ear emultiplexed withothersystemfunctions,andarecontrolledby pfc , pfd , and pmcr[2:0] .portlissharedwithlcdspecificsignalsof lcdc.turningofflcdcbysetting lpwr ( lctr[7] )reserves portlforgpio. selectingrespectivepinstobegpioorsignalsof system functionwillnotaffectoriginalsettingsofi/od irectionsand types.thisentendstheflexibilityoftheusageof function signals. note:allthepropertiesofpinsarestillprogramm able andmustbeascertainedbeforetheyare assignedtosystemfunctions,especiallythe directionofpins. figure 7-2 configuration of port-c ST2205U version1.0 10/32 6/13/2007 8 8 . . c c h h i i p p - - s s e e l l e e c c t t l l o o g g i i c c ( ( c c s s l l ) ) theST2205Ubuildsinonechipselectsignal( cs0 )for embedded16kbytesmaskromandsixchipselectsig nals multiplexedwithpd5~0ofportdwhichareusedto select devicesontheexternalbus.therearetwooptions forthefirst 16kbytesmemorywhicharecontrolledbymmdpin.t iemmd togroundtoselectnormalmodeandenableinternal romfor thefirst16kbytesmemory.connectmmdtochipsel ectofan externaldevicetoselectemulationmodeanddisabl einternal rom.afterresetcycles,mmdchangestoanoutputa nd outputschipselectsignal cs0 .refertofigure81fortwo connectionsofdifferentmodes. twobits csm[1:0] ofportmiscellaneousregister( pmcr ) selectfourmodesofcslwhichdefinethememorysi zeof eachexternalchipselect.chipselectsignal cs6 canchange tobeaddresssignala23tomakeonesingledevice of16m bytesat cs5 possible.theaddressrangeof csx ofhigher numberfollowstherangeofpreviousoneoflowern umber. note:write1tobitofportdirectioncontrol register pcd ,thentobitofport functionselectregister pfd toactivatethe designatedchipselectsignal. a. normal mode b. emulation mode figure 8-1 connections of mmd/ cs0 ST2205U version1.0 11/32 6/13/2007 9 9 . . t t i i m m e e r r / / e e v v e e n n t t c c o o u u n n t t e e r r 9.1 prescaler 9.1.1 function description theST2205Uhasfour12bittimers,eightbasetime rswith7 fixedtimerbasesandoneadjustable.thereisapr escalerthat generate6differentclocksouretosupportthetim erscounting tointerrupt. figure 9-1 structure of two prescalers 9.1.2 pres theprescalerpresisan8bitscounterasshownin figure 91. which provides six clock sources for 12bit up counting timer. it is controlled by register prs. the instru ction read towardprswillbringoutthecontentofpresandt he instructionwritetowardprswillresetorenablep res. table 9-1 prescaler control register (prs) address name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default r prs[7] prs[6] prs[5] prs[4] prs[3] prs[2] prs[1] prs[0] 00000000 $29 prs* w sres sena 00 read bit7~0: prs[7~0] : valueofprescounter write bit7: sres : prescalerresetbit write1toresettheprescaler(prs[7~0]) bit6: sena : prescalerenablebit 0=disableprescalercounting 1=enableprescalercounting ST2205U version1.0 12/32 6/13/2007 9.2 base timer thebasetimersupportsoneinterrupt,whichoccurs atseven differentfixedratesandoneadjustableclock.app licationsbase onthebasetimerinterruptcanchoseanappropriat einterrupt ratefromeighttimebasesfortheirspecificneeds .these realtimeapplicationsmayincludedigitizersampli ng,keyboard debouncing,orcommunicationpolling.blockdiagram ofbase timerisshowninfigure92. control register base timer interrupt 2hz counter 8192hz counter frequency divider btc[7~0] 1024hz counter 512hz counter 256hz counter 128hz counter 64hz counter 32hz counter oscx figure 9-2 base timer block diagram 9.2.1 base timer operations thebasetimerconsistsofeightsubcountersando nedivider toproduceeightpredefinedrates.theconnections between overflowsignalsofthesesubcountersandthebase timer interruptarecontrolledbyrespectivebitfieldso fbasetimer enableregister( bten ).theenabledoverflowsignalsare oredtogeneratethebasetimerinterruptrequest. relatedbits ofbasetimerstatusregister( btsr )willshowwhichratesof interruptsshouldbeserviced.write1toeachbi tofthe registermaycleareachbitoftheregisterrespect ively. note:makesure btsr isclearedaftertheinterrupt wasserviced,sothattherequestcanbesetnext time. ST2205U version1.0 13/32 6/13/2007 1 1 0 0 . . p p s s g g 10.1 function description thebuiltinfourchannelprogrammablesoundgenera tor (psg)iscontrolledbyregisterfiledirectly.its flexibilitymakesit usefulinapplicationssuchasmusicsynthesis,sou ndeffects generation,audiblealarmsandtonesignaling.ino rderto generatesoundeffectswhileallowingtheprocessor toperform othertasks,thepsgcancontinuetoproducesound afterthe initialcommandshavebeengivenbythecpu.thest ructureof psgwasshowninfigure101andfigure102.each channelofpsgoftheST2205Uhasthreeplayingtyp e.one forsquaretypetonesoundplaying.secondfordac pcm playing.thethirdsoundplayingtypeisdacadpcm playing. thethreetypecanbeappliedinthefourchannels andmixed tooneoutputsignaltomakethepsggeneratesmelo dyand voiceatthesametime. figure 10-1 psg one channel structure block figure 10-2 psg four channel mixer structure block ST2205U version1.0 14/32 6/13/2007 10.2 tone generator thetonefrequencyisdecidedbytimerandthevolu meis controlledbydacdataoutputregister(psgxa).besi des dacdatacanbeusedtoadjustvolume,thetwoleve l volumecontrol(volx&volmx)areeffective,too.so its veryflexibletogenerateanytonesoundwhichyou want. forexample:ifthe1khztonesoundwanttobegene rated onchannel0andthevolumeismaximum.first,thet imer0 mustbesetup2khzandwriteffhtodacdata(psga 0). second,thetwolevelvolumecontrolareadjusting to maximum.. 10.3 pcm dac abuiltinpwmdacisforanalogsamplingdataorv oice signals.thereisaninterruptsignalwhichiscont rolledby timerformdactocpuwheneverdacdataupdateis neededandthesamesignalwilldecidethesampling rateof voice.eachchannelhasa16bytefifo.whenthefi fo emptybyteismorethan8,thetimerinterruptwill be triggered.besides,therearetwostepsvolumecont rolto adjustonechannelintegratevolumeandacoupleof channelsintegratevolume.refertodescriptionof following table. 10.4 adpcm dac adpcmisakindofencodeofvoicecompression.the compressiondatausuallyisanindex.itsthrough theindex togetanoffsetvalueofthepresentvoicesample data.in adpcmdacmode,wejuststoretheoffsetvalueto registerpsgxatoaddtopresentvoicesampledata, or storetheoffsetvaluetoregisterpsgxbtosubtrac tto presentvoicesampledata. multiplicator ST2205Ubuildina16x8multiplicatorforwavetabl e operation.wejustwritetwicetomulhthatfirst is multiplicandlowbytethenhighbyteandmullis multiplier.afterthemultiplieriswrittenandwai t6opcycle, theanswersbit23~8canbereadfrommulhandm ull, thebit7~0isignored.besides,theanswerwasrelo adedto multiplicandautomaticallywhentheanswerhasappe ared. 10.5 pwm dac output mode options thepwmdacgeneratorhasthreemodes,singlepin mode,twopintwoendedmodeandtwopinpushpull mode.theyaredependedontheapplicationused.th e dacmodeiscontrolledbypsgo[1~0]ofregister psgc[2~1].. 10.5.1 single-pin mode (8-bit accuracy) singlepinmodeisdesignedforusewithasinglet ransistor amplifier.ithas8bitsofresolution.thedutycy cleofthe psgobisproportionaltotheoutputvalue.iftheo utput valueis0,thedutycycleis50%.astheoutputva lue increasesfrom0to127,thedutycyclegoesfromb eing high50%ofthetimeupto100%high.asthevalue goes from0to128,thedutycycledecreasesfrom50%h ighto 0%.psgoisinverseofpsgobswaveform.figure13 3 showsthepsgobwaveforms. ST2205U version1.0 15/32 6/13/2007 1 1 1 1 . . l l c c d d thelcdcontroller(lcdc)providesdisplaydataand specificsignalsforexternallcddriverstodrive thestn lcdpanels.thelcdcfetchesdisplaydatadirectly from internaldisplaybufferthroughoneuniquememoryb us.the specialdesignedinternalbussharesalmostnoneof the cpuresourcestomakebothfastdisplaydataproces sand highspeedcpuoperationpossible. ST2205Usupportthreedisplaymodesincluding blackandwhite,4grayleveland16grayleveland is selectedby gl[3:2] ofcontrolregister lctr .further,it throughpwm+frctechniquethatselectedby gl[1~0] to generate31graylevelsandprovidesonepalette lpal($4c) tochoose16graylevelswhichmakethe 4grayleveland16graylevelmoresmoothlythano nly frc. theST2205Ubuildsin32kbytessram,sothemaximu m panelsizecanbe640x400forb/w,400x320for 4grayleveland160xrgbx120for16graylevelmode . lcdckisforlcdctogeneratetimingsandthepixel clock. theST2205Usupports1bit,4bitand8bitdatabu sforthe compatibilityofmostpopularlcddrivers.thelcd output signalsaresharedwithportl,andarecontrolled bylcd powercontrolbit lpwr ( lctl[7] )anddatabusselection bits lmod[1:0] .incaseof1bitmode,pl2~1canstillbe usedforgeneralpurposewhileonlypl0outputslcd data. note: a. thelcdsignalswillbedisconnectedand portlwilloutputvaluesassignedby pl aftersetting lpwr . b. set pl =00htomakeportloutputzeros whenlcdcisoff. variousfunctionsarealsosupportedtorichthedi splay information,includingvirtualscreen,panning,scr olling, contrastcontrolandanalternatingsignalgenerato r.control registersusedbylcdcarelistedbelow. 11.1 lcd specific signals thefollowingsignalsaregeneratedbylcdctoconn ect theST2205Uandanlcdmodule.twoofthemare dedicatedoutputpins,whiletherest13pinsares hared withportlandporte flm (pl7) thelcdframemarkersignalindicatesthestartof anew displayframe.flmbecomesactiveafterthelastli nepulse oftheframeandremainsactiveuntilthenextline pulse,at whichpointitdeassertsandremainsinactiveunti lthenext frame. lp1 (pl6) thelcdlinepulsesignalisusedtolatchalineo fshifted datatothesegmentdriversoutputsandisalsous edto shiftthelineenablesignalofcommondriver.all thedriver outputsthencontroltheliquidcrystaltoformthe desired frameonpanel. ac (pl5) thelcdalternatesignaltogglesthepolarityofli quid crystalonthepanel.thissignalcanbeprogrammed to toggleforaperiodof1to31linesoroneframe. cp thelcdshiftclockpulsesignalistheclockoutpu ttowhich theoutputdatatothelcdpanelissynchronized.d atafor segmentdriversisshiftedintotheinternallineb ufferat eachfallingedgeofcp. ld7~0 (pe6~3, pl3~0) thelcddatabuslinestransferpixeldatatothel cdpanel sothatitcanbedisplayed.threekindsofdatabu sses,1, 4and8bit,aresupportedandarecontrolledby lmod[1:0] ( lckr[5:4] ).incaseof1bitmode,lcdcusesonlyld0to transferdata.ld3~1canstillbeprogrammedtobe normal inputsoroutputs.theoutputpixeldatacanbeinv erted throughprogramming.setting rev ( lctr )willreversethe outputdataondatabus. poff (power control) thelcdpowercontrolsignalisusedtoturnon/off the externaldcdcconverter,whichgeneratesahighvo ltage fordrivingliquidcrystal. poff outputs1whenclearing lpwr ( lctr ),andoutputs0bysettingthisbit,whichis alsothedefaultvalue. blank (contrast control) thelcdblanksignalisusedtocontrolthecontras tof displaybysettingcontrastlevelin lpwm[5:0] with00000 (default)representsamaximumleveland11111is for minimum.the blank signalachievesthisfunctionby outputtingapwmsignalaccordingtothesettingso f contrast. besidescontrastcontrol, blank signalplaysanotherrole ofturningdisplayoff.thisiscontrolledbyregis terbit blnk ( lctr[6] ).setting blnk willmake blank signalto output0toblankthedisplayregardlessofcontr astcontrol. setting blnk bitwillenablethepwmcontrastcontroland ofcoursethe blank signal.if lpwm[5:0] areallzeros, blank signalwillstayathighlevelwithnopwm modulation. lp2 (pe7) whenpwmgraylevelfunctionisenabledbysetting gl[1:0] ( lctr[4]) ,thepwmlinepulsesignalwillbe outputtedfromthispin.whenthisfunctionisoff ,lp2 outputstheidenticalsignalwiththatoflp1. ST2205U version1.0 16/32 6/13/2007 11.2 mapping the display data thescreenwidthandheightofthelcdpanelare programmablethroughsoftware.althoughthemaximum screensizecanbeupto1024x512,theactualsuppo rted resolutionislimitedbythedisplaybuffersize,w hichisalso theinternalramsize,andis32kbytes.insteadof screen sizespecifiedbycontrolregisters,largerframec analsobe displayedviathevirtualpagewidthsetting.figur e111 illustratestherelationshipbetweentheportionof alarge graphictobedisplayedonthescreenandtheactua larea thatcanbeseen. eachoneortwoevenfourbitsinthedisplaymemor y correspondtoapixelonthelcdpanel.table111 shows themappingofthedisplaydatatothepixelonlcd .when clearcontrolbits gl[3~2] ( lctr[3~2] )andenableb/w mode,everybitofdisplaybufferrepresentsonepi xelonthe screen.incaseof4graylevelmode,thereneedst wobits topresenteachpixelonthescreen.andthereneed s4bits for16graylevelmodetodisplayonepixel. figure 11-1 lcd screen format table 11-1 mapping memory data on the screen a. 1-bit-per-pixel mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 pixel [0,0] pixel [1,0] pixel [2,0] pixel [3,0] pixel [4,0] pixel [5,0] pixel [6,0] pixel [7,0] pixel 8,0] pixel [9,0] : : : : : : : : : : b. 2-bit-per-pixel mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit6 pixel [0,0] pixel [1,0] pixel [2,0] pixel [3,0] pixel [4,0] : : : : : c. 4-bit-per-pixel mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pixel [0,0] pixel [1,0] : : ST2205U version1.0 17/32 6/13/2007 11.3 lcd interface timing thelcdcontrollercontinuouslypumpsthepixeldat ainto thelcdpanelviathelcddatabus.thebusistime dby thecp,load,andflmsignals.twokindsofdatawi dth,1 and4bit,aresupportedformostmonochromelcdpa nels. refertofigure112forboth1and4bitinterfac etiming. figure 11-2 lcd interface timing for 1-/4-bit data ST2205U version1.0 18/32 6/13/2007 1 1 2 2 . . s s e e r r i i a a l l p p e e r r i i p p h h e e r r a a l l i i n n t t e e r r f f a a c c e e theST2205Ucontainsoneserialperipheralinterfac e(spi) moduletointerfacewithexternaldevices,suchas flash memory,analogtodigitalconverter,andotherperi pherals, includinganotherST2205U.thespiconsistsofama ster orslaveconfigurableinterfacesothatconnections ofboth masterandslavedevicesareallowable.fivesignal s multiplexedwithportcareusedbyspi.withequip ped data_ready and ss (slaveselect)controlsignalsand transmit/receivebuffers,fasterdataexchangewith fewer softwareinterruptsiseasytobemade.datalength is widelysupportedfrom7bitupto16bittosatisfy various applications.oneclockgeneratorisprovidedfort he synchronouscommunicationclocksck,whichissourc ed fromosck.figure121illustratestheblockdiagra mof spi. cpuinterface clock generator 16bitshiftregister (msbfirst) 16bittransmit buffer 16bitreceive buffer mosi miso interface control sck osck data_ready spick ss figure 12-1 spi block diagram 12.1 spi operations thespicontainsone16bitshiftregisterandtwo 16bit buffersfortransmissionandreceivingrespectively .data withvariablelengthfrom7bitto16bitcanbeex changed withexternaldevicesthroughtwodatalines.data lengthis controlledbybitcountregister bc[3:0] (bit3~0ofspiclock controlregister sckr) .thecurrentexchangewillbeover whiletheexchangedbitnumberreachesbitcountse tting. thesynchronouscommunicationclocksckisusedto synchronizetwodevicesandtransferdatainandou tofthe shiftregister.dataisclockedbysckwithaprogr ammable datarate,whichisassignedby sck[2:0] (bit6~4ofspi clockcontrolregister sckr ).thespiblockiscontrolledby spien ( sctr[7] ).setting spien willenablespifunction andtheclockdivider.thentheinternalstatesof spiwillbe resettoinitialvalues.afterthat,writedatato sdatal will initiateanexchange.whileexchanging,thebusyfl agwill besetandisreportedin sbz (bit4ofspistatusregister ssr ). aslaveselectsignal ss (multiplexedwithpc4)isusedto identifyindividualselectionofaslavespidevice .slave devicesthatarenotselecteddonotinterferewith spibus activities.foramasterspidevice, ss canbeusedto indicateamultiplemasterbuscontentionwhichcan be reportedinmodefaultbit mderr (bit3ofspistatus register ssr ). ST2205U version1.0 19/32 6/13/2007 1 1 3 3 . . u u n n i i v v e e r r s s a a l l a a s s y y n n c c h h r r o o n n o o u u s s r r e e c c e e i i v v e e r r / / t t r r a a n n s s m m i i t t t t e e theST2205Uintegratesoneuniversalasynchronous receiver/transmitter(uart),whichcanbeusedto communicatewithexternalserialdevices.serialda tais transmittedandreceivedatstandardbitratesusin gthe internalbaudrategenerator(bgr),whichiscontro lledby bgrcontrolregister bctr .settingsofclockoutputof bgr(bgrck)canbefoundinsection9.figure131 showstheblockdiagramofuart.summaryofuart controlregistersislistedinfigure131 cpuinterface baudrate generator transmitter receiver txd0 rxd0 serial interface irda interface txd1 rxd1 figure 13-1 uart block diagram 13.2 uart operations theuarthastwomodesofoperation,nrzandirda, whichrepresentdataindifferentwaysforserial communicationprotocols,rs232andirda. 13.2.1 nrz mode thenonreturntozero(nrz)modeisprimarilyasso ciated withrs232.eachcharacteristransmittedasafra me delimitedbyastartbitatthebeginningandasto pbitatthe end.databitsaretransmittedleastsignificantbi t(lsb)first, andeachbitoccupiesaperiodoftimeequalto1f ullbit.if parityisused,theparitybitistransmittedafter themost significantbit.datasettingsincludingdatalengt h,stopbit numberandparityarecontrolledbybitfieldsin uctr . figure132illustratesacharactersinnrzmode . 13.2.2 irda mode irdamodeusescharacterframesasnrzmodedoes,b ut, insteadofdrivingonesandzerosforafullbitti meperiod, zerosaretransmittedasthreesixteenth(orless) bittime pulses(whichisselectedby pw[1:0] ( irctr[2:1] ),and onesremainlow.thepolarityoftransmittedpulses and expectedreceivepulsescanbeinvertedsothatad irect connectioncanbemadetoexternalirdatransceiver modulesthatuseactivelowpulses.thisiscontrol ledby rxinv and txinv ( irctr[7:6] ).irdamodeisenabledby controlbit iren ( irctr[0] ).figure133illustratesa charactersinirda bit0 startbit 1 23 4 5 6 bit7 paritybit stopbit figure 13-2 nrz ascii s with odd parity bit0 startbit 1 23 4 5 6 bit7 paritybit stopbit figure 13-3 irda ascii s with odd parity ST2205U version1.0 20/32 6/13/2007 1 1 4 4 . . u u n n i i v v e e r r s s a a l l s s e e r r i i a a l l b b u u s s ( ( u u s s b b ) ) theST2205Uincorporatesonepll,a3.3vregulator, and ausb2.0fullspeeddeviceenginetosatisfythes trong demandoffastdatatransferfrommarket.bothhid and massstorageclassesaresupportedaswellasthef irmware librariesandthewindows98driver.wholeusbfunc tionis controlledbysetting usben ( usbcon[7] ).afterconnects toausbhostport,6interruptswhichsharethesa me interruptvectorplaythemainroleofusbcommunic ation. properroutinesrespondingtoeveryhostcommandsh ould beexecutedtogeneratetherightanswerintothee ndpoint bufferstobetransferredback. threeendpointsaresupportedincludingcontrolend point (ep0),bulkinendpoint(bki)andbulkoutendpoint (bko). ep0hasabufferof8byteslongwhilebkiandbko each hasa64bytesbufferwhichthreerangefrom$200t o$28f. refertotable141forthememorymapping.write 1to bufen ( usbien[7] )toenablethesebuffers.therearestill total144bytesofuserramtousewhenusbbuffer is hiddenbyclearing bufen . doublebufferschemeisappliedtobothbkiandbko bufferstoincreasethroughputandeasesrealtime data transfer. table 14-1 summary of usb buffers buffer address bko $200~$23f bki $240~$27f ep0out $280~$287 ep0oin $288~$28f ST2205U version1.0 21/32 6/13/2007 1 1 5 5 . . d d i i r r e e c c t t m m e e m m o o r r y y a a c c c c e e s s s s ( ( d d m m a a ) ) tospeedupthedatatransfer,dmaworksefficientl ywithout cpuinvolvedandmovesonebyteofdatainonlytwo sysckcycles.afterawriteto dcnth ,cpupausesand thendmastarts.meanwhiletheaddressanddatabus is freedfordmajob.ineachtransfer,upto32kbdat acanbe moved.onlysingleinstructionisneededforarepe ated transfer.itcantheoneofthreeasbelow: a. stzzp(3 cycles) b. smb7zp(5cycles) c. rmb7zp(5cycles) dmaworksonlyonthelogicaladdressof$8000~$fff f, combineswithsourceanddestinationbankregisters ,all physicalmemorycanbeaccessedincludingwhole32k b internalramifbit16ofbankregisterisset. note: ifbit16ofbankregisterisset,$8000~$807fwill refertocontrolregisters therearetwodmachannelsandareselectedby dmsel[1] ( dctr[1] ).afterselectingachannel,sourceor destinationregistersarethenchoseby dmsel[0] ( dctr[0] ) tomakefurtherregisteraccesscorrect. 15bitsourcepointer: dptr ( dmsel[0] =0) 15bitdestinationpointer: dptr ( dmsel[0] =1) 11bitsourcebankregister: dbkr ( dmsel[0] =0) 11bitdestinationbankregister: dbkr ( dmsel[0] =1) 15bitdatalengthregister: dcnt therearethreemodesformanipulationofbothpoin ters: a. continue, b. reload,and c. fixed.pointerincreasesone aftereachtransferincontinuemode,andbecomes$ 8000 after$ffffisreached.atthistime, dbkr alsoincreases onetomaptothenextbank.reloadmodeactslike continuemodeexceptpointerandbankregisterswil lback totheiroriginalvalueswheneachtransferstops. incaseof fixedmode,pointerkeepsthesamevaluealways. exceptingnormaloperation,thereisonespecialfu nction foreachchannel,andiscontrolledby func[1:0] ( dmod[5:4] ).dmachannel0canhelpimage dataoperations.and,orandxorlogicoperationsc anbe donebetweensourceanddestinationdatabeingmove d. regardingchannel1,doubledatatransferspeedisp ossible whilemovingdatafrom/tonandflashviaportf. ST2205U version1.0 22/32 6/13/2007 1 1 6 6 . . n n a a n n d d f f l l a a s s h h i i n n t t e e r r f f a a c c e e theST2205Uhasasimplifiednandflash(flashfors hort inthefollowing)interfaceforbothandandnandt ypes whichonly9or10specificsignalsareneeded.com bine othergpios,thisserialinterfacecarriescommands and databetweenmcuandflashmemorybycpuread/write instructionsorbydmachannel1. datamovedbydmachannel1mayhasecccodes generatedatthesametime.whendatawritetoflas his performed,ecccodeswillbereadyattheendof transmission,thentheyaretobewrittentoflash and storedintheredundantarea.incaseofdataread, ecc codescalculatedbymcuaretobecomparedwiththo sein redundantareaandcheckifthereisanybiterror, even correctthiserror. 16.1 nand flash interface, port-f flashmemoryisaserialaccessedmemory.typical interfacesignalsforandandnandtypesarelisted in figure161aswellastheconnectionwithST2205U. if fen ( fctr[7] )isset,portfwillbethe8bitserialdatabus andpd7/ fwr ,pd6/ frd willplaywrite/readsignals, whileothercontrolsignalsarecontrolledby csx ,intxx andgpios.theandtypeflashinterfaceneedsonly pd7 andfurthersavespd6forgpio.sincenandflash interfacehashigherpriority,pd7/6willbe fwr / frd signalsif fen =1,regardlessofsettingsof pfd .portf worksthesameway,i/odirectionswillnotbecont rolledby pcfbutbyread/writeaccessofdatawhenflashint erface enabled.itisfloatingwhennotbeingaccessed,ou tput whenwritetoportfandisinputwhenreadfrompo rtf. figure 16-1 connecting nand and and flash memories 16.2 error correction code (ecc) ecccodeconsistsof3bytesper256bytesofdata. the xoredresultofnewandoldecccodesshowsifther eisa biterrorbetweentwo256bytesofdata,eventhel ocationof theerrorbit.twosetsofecccodes, ecc0 and ecc1 ,are supportedandareselectedby eccsel .soresultsofupto 512bytescanbeprocessedandstored.threebytes of eachcanbeaccessedatthreeregisters eccl/m/h . therearetwowaystotriggerecccalculation.firs tis executeread/writetopfwhen eccen =1and pfecc =1. secondismovingflashdataviadmachannel1.ecco f first256byteswillbecalculatedfirstin ecc0 ,andthen changesto ecc1 automaticallyforthoseafter256.the calculationstopsafter512bytesarereachedeven there arestillmorebeingmoved. beforeflashdatatransfer,clearecccodesandthe counterbywriting1to eccclr .afterwriteof512bytes isperformed,control eccsel andgettheresultsfrom ecc0 and ecc1 .incaseofreadtransfer,afterreading512 bytes,retrievetwo3byteecccodesintheredunda ntarea andwritetheminto ecc0/1 respectively.eachwriteto eccl/m/h willmakeaxoroperationbetweentheoriginal dataandthebytewritteninto.after ecch iswroteabyte, ecccheckingstarts.theresultwillbereportedat fsr[1:0] inonesysckcycle.meanwhile eccl/m/h alsoreportthe errorbitpositionifthereisone. ST2205U version1.0 23/32 6/13/2007 1 1 7 7 . . p p o o w w e e r r d d o o w w n n m m o o d d e e s s ST2205Uhasthreepowerdownmodes:wai0,wai1an d stp.theinstructionwaiwillenableeitherwai0o rwai1, whichiscontrolledby wait ( sys[2] ).andtheinstruction stpwillenable stp modeinthesamemanner.wai0and wai1modescanbewakedupbyinterrupt.however, stp modecanonlybewakedupbyhardwarereset. 17.1 swai-0 mode: if wait iscleared,waiinstructionmakesmcuenterwai0 mode.inthemeantime,theoscillator,interrupts, timer/counter,andpsgarestillworking.ontheot herhand cpuandtherelatedinstructionexecutionstop.all registers, ram,andi/opinswillretainthesamestatesasth ose beforethemcuenteredpowerdownmode.wai0mode canbewakedupbyresetorinterruptrequesteven ifuser setsinterruptdisableflag i .inthatcasemcuwillbewaked upbutnotenteringinterruptserviceroutine.ifi nterrupt disableflagiscleared( i =0),thecorrespondinginterrupt vectorwillbefetchedandtheserviceroutinewill be executed.thesampleprogramisshownbelow: lda #$00 sta ST2205U version1.0 25/32 6/13/2007 1 1 9 9 . . r r e e a a l l t t i i m m e e c c l l o o c c k k 2 2 0 0 . . l l o o w w v v o o l l t t a a g g e e d d e e t t e e c c t t o o r r ( ( l l v v d d ) ) ST2205Uhasabuiltinlowvoltagedetectorforpow er management.twovoltagesignalscanbeselectedby the controlbit lvds ( lvctr[1] ).firstisthepowerappliedto ST2205Uandhasfourdetectionlevelscanbeselect edby lvd[1:0] ( lvctr[3:2 ]).secondisthesignalappliedto inputpinvin,andhasfourdetectionlevelscanbe selected, too.when lvden ( lvctr[0] )isset,lvdisenabledand thedetectionresultwillbeoutputtedatthesame bitafter 30us.usingreadinstructiontwicecangetthisres ult:first readwillenableinitialstablenesscontrol.second read equal'0'represents'lowvoltage'.oncelvdisena bled,it keepsonconsumingpower.soitisimportanttowri te0to lvden and disablethedetectorafterdetectionis completed.infigure201showsanapplicationcirc uitfor detectingbatteryvoltageappliedtovin( lvds=1 ).note thatthedccurrentoftwoexternalresistorscanb ecutoff bysettingpc0toopen.alsoaddonecapacitortov into minimizenoiseandnarrowthelowvoltagedetection range. infigure202showsanotherapplicationcircuit.i twill consumeaconstantcurrentbutsavethedelaytime forvin tobestable.if lvds=0 anddetectingvdd,pleaseleave vinpinopen. figure 20-1 application of lvd (1) figure 20-2 application of lvd (2) 2 2 1 1 . . l l o o w w v v o o l l t t a a g g e e r r e e s s e e t t ( ( l l v v r r ) ) powerbouncingduringpoweronisamajorproblemw hen designingareliablesystem.theST2205Uequipslow voltageresetfunctiontokeepwholesysteminrese tstatus whenpowerisnotstable.oncelowvoltagestatusi s detected,anactivelowpulsewillbeoutputfromp in reset toperformthisprotection.afterthepowerbacks tonormal,willoutputhighandthesystemmayreco verits originalstatesandkeepsworkingcorrectly. thelvrcircuitalwaysworksanditconsumesveryf ew current. ST2205U version1.0 26/32 6/13/2007 2 2 2 2 . . e e l l e e c c t t r r i i c c a a l l c c h h a a r r a a c c t t e e r r i i s s t t i i c c s s 22.1 absolute maximum rations dcsupplyvoltage 0. 3vto+4.5v operatingambienttemperature 10 cto+60 c storagetemperature 55 cto+125 c 22.2 dc electrical characteristics standardoperationconditions:vcc =3.0v,gnd=0v,t a =25 c,osc=8mhz(cpuclock=4mhz),unlessotherwise specified parameter symbo l min. typ. max. unit condition operatingvoltage vcc 2.4 3.6 v operating frequency(osc) f 1 12 mhz vcc=2.4v~3.6v(cpuclock=6mhz) operating frequency(osc) f 2 16 mhz vcc=3.0~3.6v(cpuclock=8mhz) operatingcurrent i op 6.1 ma alli/oportareinputandpullup,executenop instruction,lcdcon standbycurrent i sb0 1200 a alli/oportareinputandpull up,oscxon,lcdcon (wait0mode)seg=240,cp=sys,lfra=30 28 38 a alli/oportareinputandpullup,oscxon,heavy load,lcdcoff (wait1mode)lvr=2.8v standbycurrent i sb1 16 21 a alli/oportareinputandpullup,oscxon,heavy load,lcdcoff (wait1mode)lvr=2.1v 19 25 a alli/oportareinputandpullup,oscxon,normal load,lcdcoff (wait1mode)lvr=2.8v standbycurrent i sb2 7 10 a alli/oportareinputandpullup,oscxon,normal load,lcdcoff (wait1mode)lvr=2.1v 15 20 a alli/oportareinputandpull up,oscxoff,lcdcoff (wait1mode)lvr=2.8v standbycurrent i sb3 3 5 a alli/oportareinputandpull up,oscxoff,lcdcoff (wait1mode)lvr=2.1v inputhighvoltage v ih 0.7vcc v porta/b/c/d/e/l inputlowvoltage v il 0.3vcc v porta/b/c/d/e/l pullupresistance r i h 90 k porta/b/c/d/e/l(inputvoltage=0.7vcc) outputhighvoltage v oh 1 0.7vcc v porta/b/c/d/l (i oh =4.5ma) outputlowvoltage v ol 1 0.3vcc v porta/b/c/d/e/l(i ol =6.5ma) outputhighvoltage v oh 2 0.7vcc v psg/dac,i oh =40ma. outputlowvoltage v ol 2 0.3vcc v psg/dac,i ol =40ma. *note: stresses above those listed under "absolute maximum ratings"maycausepermanentdamagetothedevice. allthe ranges are stress ratings only. functional operatio n of this deviceattheseoranyotherconditionsabovethose indicated intheoperationalsectionsofthisspecificationi snotimpliedor intended.exposedtotheabsolutemaximumratingco nditions forextendedperiodsmayaffectdevicereliability. ST2205U version1.0 27/32 6/13/2007 currentdacouput iout 3 ma 4095 th step lowvoltageresetlevel v lvr1 1.8 1.9 2 v pinoptionlvrsel=0 lowvoltageresetlevel v lvr1 2.55 2.65 2.75 v pinoptionlvrsel=1 lowvoltagedetect current i lvr 38 60 a totallvdcircuitcurrentconsumption lowvoltagedetectlevel v lvr1 2.2 2.4 2.6 internalmodelvds[1:0]( lvctr[3:2] )=00 lowvoltagedetectlevel v lvr2 2.4 2.6 2.8 internalmodelvds[1:0]( lvctr[3:2] )=01 lowvoltagedetectlevel v lvr3 2.6 2.8 3.0 internalmodelvds[1:0]( lvctr[3:2] )=10 lowvoltagedetectlevel v lvr4 2.8 3.0 3.2 internalmodelvds[1:0]( lvctr[3:2] )=11 lowvoltagedetectlevel v lvr5 1.1 1.2 1.3 externalmodelvds[1:0]( lvctr[3:2] )=00 lowvoltagedetectlevel v lvr6 1.2 1.3 1.4 externalmodelvds[1:0]( lvctr[3:2] )=01 lowvoltagedetectlevel v lvr7 1.3 1.4 1.5 externalmodelvds[1:0]( lvctr[3:2] )=10 lowvoltagedetectlevel v lvr8 1.4 1.5 1.6 externalmodelvds[1:0]( lvctr[3:2] )=11 0.3 s 32768crystalheavymode. warmuptime t wm1 3 s 32768crystalnormalmode. 8 ms mainfrequencycrystal8192warmupcycle warmuptime t wm2 12 ms mainfrequencycrystal32768warmupcycle 20 us mainfrequencyrosc16warmupcycle warmuptime t wm3 80 us mainfrequencyrosc256warmupcycle ST2205U version1.0 28/32 6/13/2007 ac electrical characteristics figure 22-1 external read timing diagram figure 22-2 external write timing diagram table 22-1 timing parameters for figure 22-1 and fi gure 22-2 standardoperationconditions:vcc =3.0v,gnd=0v,t a =25 c rating symbol characteristic min. typ. max. unit tsa addresssetuptime 10 ns tha addressholdtime 0 ns twlc cslpulsewidth 166 ns tclwl csassertedto r w asserted 1/2twlc ns twhch csnegatedafter r w isnegated 10 ns tsdw csassertedtodataoutisvalid 1/2twlc ns thdw dataoutholdtimeafter r w isnegated 20 ns tclrl csassertedto d r asserted 1/2twlc ns trhch csnegatedafter d r isnegated 10 ns tsdr datainvalidbefore d r isnegated 30 ns thdr datainholdtimeafter d r isnegated 10 ns tr signalrisetime 20 ns tf signalfalltime 10 ns ST2205U version1.0 29/32 6/13/2007 2 2 3 3 . . a a p p p p l l i i c c a a t t i i o o n n c c i i r r c c u u i i t t s s flm blank poff lp1/2 ac cp ld[7:0] pb[7:0] pa[7:0] psgo psgob 100 a0 d[7:0] cs! rd wr rd wr txd0 rxd0 rs232 csx vin pc0 usb d d+ usbvss vbus rpull note:1.keepthetracebetweenoscillationresisto randthepcbpadascloseas possibleforamorestableclock. 2.theoscxcanstillworkifremovecx1andincrea secx2to47pf. 3.thecapacitorsthatconnecttovout3.3,pllvdd, usbvddmustascloseas possibletoreducenoises. 4.resisterrpandzenordiodezdprovideasolutio nforusinghostpowerwhen usbcablepluggedin. ST2205U version1.0 30/32 6/13/2007 2 2 4 4 . . o o t t p p r r o o m m p p r r o o g g r r a a m m m m i i n n g g i i n n t t e e r r f f a a c c e e 24.1 interface description inordertoprogramotprom,severalpinshavetob e reservedonthepcbwhichisboundingwithST2205U. thesetotalsare34pinsthatincludefollowinglis ttable 241.itjustbeusedtoconnectwritertoprogram otp rom. table 24-1 pin assignment of interface pad name pin type description vpp power high voltage power supply 1) otp program, program verify, test modes. 9v 2) otp read: vpp need connect to vdd vdd power vss power resetb input test2 input pl6 input pl5 input pl4 input pl3 input pl[2:0] input i/o data[7:0] i/o address[13:0] input ST2205U theaboveinformationistheexclusiveintellectual propertyofsitronixtechnologycorp.andshallno tbedisclosed,distributedorreproducedwithout permissionfromsitronix. sitronixtechnologycorp .reservestherighttochangethisdocumentwithou tpriornoticeandmakesnowarrantyforany errors which may appear in this document. sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similarapplicationswhereproductsfailurecouldr esultininjury,orlossoflife,orpersonalorph ysicalharm,oranymilitaryordefenseapplication ,or anygovernmentalprocurementtowhichspecialterms orprovisionsmayapply. version1.0 31/32 6/13/2007 2 2 5 5 . . r r e e v v i i s s i i o o n n s s revision description page date 1.0 addwaitingcyclefeature. 1 2005/9/26 modifyusb1.1tousb2.0fullspeek 1,2,4,20 0.1 firstrelease 2005/3/16 |
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